Job Description
About Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers from NVIDIA, Google, and Meta, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a Power Analysis Engineer to generate accurate power data and build robust analysis flows for SoC designs. You will work across verification, RTL, and physical design teams to collect activity data, run RTL/gate-level power estimation tools, and deliver detailed power profiles. A key part of this role is developing new scripts, utilities, and automation pipelines to improve accuracy, scalability, and turnaround time for power analysis. This position offers an excellent opportunity to combine EDA expertise with strong coding skills to make a direct impact on silicon performance and efficiency.
Key responsibilities
Coordinate with architects, RTL designers, and DV engineers to collect switching activity and collaterals for power estimation.
Run RTL and gate-level power estimation tools at block, subsystem, and full-chip levels.
Design and implement new automation flows and analysis scripts to improve accuracy and efficiency of power estimation.
Develop data processing and visualization tools to profile and interpret power results.
Generate and deliver representative vectors for power, IR drop, and thermal analysis.
You may be a good fit if you have (Must-have qualifications)
Strong coding skills in Python, C++ and TCL with experience building robust automation tools and analysis utilities.
Understanding of digital design principles with a focus on power estimation and analysis.
Familiarity with RTL and gate-level simulation flows, including handling SAIF, FSDB, or VCD files.
Experience integrating EDA tools into scripted workflows for repeatable, scalable analysis.
Strong attention to detail in data generation, validation and reporting.
Strong candidates may also have experience with (Nice-to-have qualifications)
Using power estimation tools such as Synopsys PrimePower, Cadence Joules, or Ansys PowerArtist.
Applying low-power techniques like clock gating, power gating, multi-voltage domains, or DVFS.
Ability to create new workloads for power, IR drop, and thermal sign-off.
Working with UPF/CPF power intent specifications in analysis flows.
Representative projects
Full-Chip Power Data Generation – Collected switching activity from DV teams and executed RTL/gate-level power estimation runs using Synopsys PrimePower for full-chip and subsystem levels.
Custom Power Analysis Tool Development – Built Python/TCL utilities for automated input preparation, result parsing, and data visualization, reducing power analysis turnaround time.
Sign-off Vector Preparation – Generated and validated workloads for IR drop and thermal analysis, ensuring strong correlation with functional simulations.
Base Compensation Range
$150,000 - $200,000
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
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